circuit Core :
  module Core :
    input clock : Clock
    input reset : UInt<1>
    output io : { flip imem : { flip addr : UInt<32>, inst : UInt<32>}, exit : UInt<1>}

    cmem regfile : UInt<32> [32] @[Core.scala 20:20]
    reg pc_reg : UInt<32>, clock with :
      reset => (reset, UInt<32>("h0")) @[Core.scala 24:23]
    node _pc_reg_T = add(pc_reg, UInt<32>("h4")) @[Core.scala 25:20]
    node _pc_reg_T_1 = tail(_pc_reg_T, 1) @[Core.scala 25:20]
    pc_reg <= _pc_reg_T_1 @[Core.scala 25:10]
    io.imem.addr <= pc_reg @[Core.scala 29:16]
    node _io_exit_T = eq(io.imem.inst, UInt<32>("h5")) @[Core.scala 38:20]
    io.exit <= _io_exit_T @[Core.scala 38:11]
    node _T = bits(reset, 0, 0) @[Core.scala 39:9]
    node _T_1 = eq(_T, UInt<1>("h0")) @[Core.scala 39:9]
    when _T_1 : @[Core.scala 39:9]
      printf(clock, UInt<1>("h1"), "pc_reg : 0x%x\n", pc_reg) : printf @[Core.scala 39:9]
    node _T_2 = bits(reset, 0, 0) @[Core.scala 40:9]
    node _T_3 = eq(_T_2, UInt<1>("h0")) @[Core.scala 40:9]
    when _T_3 : @[Core.scala 40:9]
      printf(clock, UInt<1>("h1"), "inst   : 0x%x\n", io.imem.inst) : printf_1 @[Core.scala 40:9]
    node _T_4 = bits(reset, 0, 0) @[Core.scala 41:9]
    node _T_5 = eq(_T_4, UInt<1>("h0")) @[Core.scala 41:9]
    when _T_5 : @[Core.scala 41:9]
      printf(clock, UInt<1>("h1"), "----------\n") : printf_2 @[Core.scala 41:9]

